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shiyan2
- Verilog HDL实现十进制计数器,FPGA ISE开发环境- Verilog HDL decimal counter
模60计数器
- 基于basys2的模60计数器设计，语言verilog(Design of module 60 counter based on basys2, Language Verilog)
count
- 用verilog语言编写一个计数器，改参数实现不同时间的计数器(Writing a counter in the Verilog language)
8比特的约翰逊计数器
- 用Verilog语言编写程序实现8比特约翰逊计数器(Write a program in Verilog language to implement the 8 bit Johnson counter.)
4位BCD计数器
- 用Verilog语言编程实现4位BCD计数器的功能(Write the programm with Verilog language to implement the function of 4 - bit BCD counter.)